The present invention relates to a technology for investigating (evaluating) conditions of a CMP (Chemical Mechanical Polishing) for configuring a Cu film in a damascene wiring structure, and more particularly to a substrate for evaluating the CMP that enables the CMP condition to be simply determined. For example, it relates to a CMP technology for providing damascene wiring structure having a plurality of stacked-layer wirings that is excellent in flatness and removability of Cu residue.
In a CMP process of Cu and a barrier film that is employed for forming a multi-layer (stacked-layer) wiring of an LSI, it is necessary to control a film thickness of the Cu wiring within a constant limit in a wide range from a microscopic wiring of 0.1 μm or less to a global wiring of 100 μm or so. Dishing or erosion of Cu and the barrier film that are generated in this CMP process is a large fluctuation factor of the Cu wiring thickness. Accordingly, the CMP allowing a reduction in an amount of the dishing and the erosion is desirable.
The process of forming the Cu wiring is conducted as described below. At first, a Cu diffusion barrier film is formed on a substrate having a wiring groove formed therein. Thereafter, a Cu seed film is formed. Continuously, the Cu film is formed having a thickness one and half times to three times of the depth of the wiring groove with a plating method. Thereafter, the unnecessary film is polished/removed with the CMP. That is, first of all, a slurry for Cu is employed, thereby to polish/remove the Cu film other than the portion that becomes the wiring. And, the polishing is suspended for the time being at the time point that the low-layer Cu diffusion barrier film has been exposed. Next, a slurry that is different from the slurry for Cu is employed, thereby to polish/remove the Cu diffusion barrier film.
In such a technology, the following conditions of (1) and (2) are of importance at the stage that the Cu film has been removed and the Cu diffusion barrier film has been exposed.
(1) Deterioration in flatness due to the dishing and the corrosion is small.
(2) Surplus Cu other than Cu of the portion that becomes a wiring is completely removed.
So as to satisfy these conditions, a method has been proposed which includes, in a state where Cu has been polished, partially leaving the Cu film unpolished and polishing the remaining Cu film simultaneously in polishing the barrier.
In this case, however, it is necessary to set a polishing speed of the barrier film and the Cu film to approximately 1:1.
Carrying out the CMP in such a manner allows the polishing amount of Cu in polishing the Cu diffusion barrier film to be enlarged. As a result, the flatness declines, and further, wiring resistance augments.
It is noted that in forming the multi-layer wiring of the LSI, the groundwork at the time of forming the first-layer (lowest-layer) wiring is relatively flat. However, in forming the wirings in the second layer and the more highly ranked layers (the layers more highly ranked than the first layer), a dimple and a bump is often formed on the surface due to the dishing and the erosion that are generated by the CMP for forming the low-layer wiring. Accordingly, it follows that the wirings of the second layer and the more highly ranked layers (the layers more highly ranked than the first layer) are formed on such a dimple and a bump.
Incidentally, in the CMP of the Cu films of the second layer and the more highly ranked layers, it is necessary to remove completely the surplus Cu in the dimple portion due to the formation of the low-layer wiring in order to prevent a inter-wiring short circuit from occurring. And, removing the Cu residue that locally exists in the foregoing dimple portion necessitates carrying out an over-polishing after the Cu film has been removed and the low-layer barrier film has been exposed. However, depending upon the CMP condition of the Cu film, in some cases, the longer-time over-polishing is necessitated as compared with the case that no dimple and bump exists in the low-layer wiring. As such, the dishing augments as the over-polishing time is prolonged. And, in the polishing process in which the over-polishing time of the more highly ranked layer is prolonged all the more, the dishing of the more highly ranked layer becomes larger. For this, it becomes difficult to form the wiring as designed in a case where numerous wiring layers are provided. Yet, setting the over-polishing time for each wiring layer is necessitated, which complicates a management of the process.
In an attempt to avoid such a problem, a method has been proposed of thickly forming an insulation layer in the half way of the step of forming the multi-layer wiring to carry out the CMP for its insulation layer, thereby allowing the dimple and bump of the groundwork to be flattened.
This technique, however, incurs an increase in the number of steps, which increases the cost.
In the example of JP-P2001-7114A “Semiconductor Device and Production Method thereof”, the substrate, which is obtained by forming the wiring groove on a flat substrate to form a metallic film thereupon, is employed as a tool for investigating the CMP.
However, in the evaluation employing such a substrate, no influence of the dimple and bump due to the low-layer wiring at the time of forming the multi-layer wiring as mentioned above is taken into consideration.
As mentioned above, the wafer with a wiring pattern for evaluation conventionally proposed is only a wafer obtained by forming a one-layer wiring on a flat silicon substrate. Accordingly, even though the proposed wafer is employed for investigating the condition in carrying out the CMP, an influence cannot be evaluated of the dimple and bump due to the dishing and the erosion of the low-layer wiring.
Thereupon, it is suggested that the method of forming the multi-layer wiring is employable for the purpose of evaluating an influence of the dimple and bump of the low-layer wiring.
This method, however, necessitates carrying out the CMP again, after carrying out the CMP for forming the first-layer wiring, in order to form the second-layer wiring. For this, it takes a long time to obtain the optimum CMP condition. Thereby, development efficiency declines.
In addition, in the above-mentioned method, the degree of the depth of the dimple due to the low-layer wiring at which Cu is removable, i.e. the margin for removability cannot be confirmed. For this, it is impossible to select the CMP condition having a sufficient margin for removability of the Cu residue in the dimple due to the low-layer wiring.
Thus, developing an evaluation technology that enables an influence of the dimple and bump due to the low-layer wiring to be simply evaluated allows development efficiency in the slurry for the CMP and the CMP process to be improved drastically. Further, in the production of the LSI employing the CMP condition having a wide margin allows its yield to be enhanced.